This application claims the priority of Korean Patent Application No. 2003-28176, filed on May 2, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices capable of preventing current flow caused by latch-up.
2. Discussion of Related Art
To perform a current test, a high voltage is applied to a bonding pad of a semiconductor device, which causes a current to flow in the semiconductor device. As such, defects occur in the semiconductor device, and the semiconductor device cannot operate properly.
FIG. 1 is a cross-sectional view of a layout of a conventional semiconductor device. FIG. 2 is a plane view of the semiconductor device of FIG. 1.
Referring to FIGS. 1 and 2, a P-type diffusion region 110 and an N-type diffusion region 120 are located in a first N-well NW1, and a P-type diffusion region 130 is located in an adjacent P-well PW. An N-type diffusion region 140 is located in a second N-well NW2 adjacent to the P-well PW.
A pad P1 is connected to the P-type diffusion region 110 of the first N-well NW1. A power supply voltage VDD is connected to the N-type diffusion region 120 of the first N-well NW1, and a ground voltage VSS is connected to the P-type diffusion region 130 of the P-well PW and the N-type diffusion region 140 of the second N-well NW2.
The P-type diffusion region 110 and the N-type diffusion region 120 of the first N-well NW1 and the P-type diffusion region 130 of the P-well PW, respectively, constitute an emitter, a base, and a collector of a first bipolar junction transistor (BJT) Q1. The N-type diffusion region 120 of the first N-well NW1, the P-type diffusion region 130 of the P-well PW, and the N-type diffusion region 140 of the second N-well NW2, respectively, constitute a collector, a base, and an emitter of a second bipolar junction transistor (BJT) Q2.
The first BJT Q1 is a PNP-type transistor, and the second BJT Q2 is an NPN-type transistor. Rn and Rnw represent the loads of the base and the emitter of the first BJT Q1 respectively. Rpw represents the load of the emitter of the second BJT Q2.
When a backward voltage is applied between the N-type diffusion region 120 (base B) of the first N-well NW1 and the P-type diffusion region 130 (collector C) of the P-well PW of the first BJT Q1, respectively, and then a forward voltage is applied between the P-type diffusion region 110 (emitter A) of the first N-well NW1 and the N-type diffusion region 120 (base B) of the first N-well NW1, the first BJT Q1 is activated, and a current IC1 flows through the first BJT Q1.
When performing a current test, a high voltage, i.e., a voltage higher than a voltage obtained by adding a turn-on voltage of a PN junction to the power supply voltage VDD, is applied to the pad P1, and thus the first BJT Q1 is activated.
When a backward voltage is applied between the N-type diffusion region 120 (collector B) of the first N-well NW1 and the P-type diffusion region 130 (base C) of the P-well PW of the second BJT Q2, and then a forward voltage is applied between the P-type diffusion region 130 (base C) of the P-well PW and the N-type diffusion region 140 (emitter D) of the second N-well NW2, the second BJT Q2 is activated.
When the voltage difference between the P-type diffusion region 130 (base C) of the P-well PW and the N-type diffusion region 140 (emitter D) of the second N-well NW2 of the second BJT Q2 is greater than the turn-on voltage, due to a resistor Rp, a forward voltage is applied between the P-type diffusion region 130 (base C) of the P-well PW and the N-type diffusion region 140 (emitter D) of the second N-well NW2, the second BJT Q2 is activated, and a current IC2 flows through the second BJT Q2.
Accordingly, a current path is formed between the P-type diffusion region 110 of the first N-well NW1 and the N-type diffusion region 140 of the second N-well NW2, and a current flows along the current path. This phenomenon is referred to as latch-up and causes defects in semiconductor devices.